1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a power semiconductor device having a trench gate structure.
2. Description of the Background Art
As a semiconductor device used in switching elements of a power amplifier circuit, a power circuit and the like, for example, there is known a semiconductor device including a high-voltage element such as a power metal insulator semiconductor field effect transistor (MISFET). Further, as a power MISFET, so-called “vertical” and “horizontal” ones are known. In addition, as a “vertical” power MISFET, one having a so-called trench gate structure is known.
Here, MISFET refers to an insulated gate field effect transistor in which a gate insulating film is interposed between a channel forming region (semiconductor) and a gate electrode. Note that a transistor in which a gate insulating film is formed of a silicon oxide film is typically referred to as a metal oxide semiconductor field effect transistor (MOSFET).
One in which current flows in a thickness direction of a semiconductor substrate is a “vertical” transistor, whereas one in which current flows in a surface direction of a semiconductor substrate is a “lateral” transistor.
One in which a channel for electrons is formed in a channel forming region between a source region and a drain region is referred to as an “n-type” transistor, whereas one in which a channel for holes is formed therebetween is referred to as a “p-type” transistor.
The trench gate structure refers to a gate electrode structure in which a gate electrode is provided, via a gate insulating film, inside a channel provided on a main surface of a semiconductor substrate.
In MOSFETs having the trench gate structure, cells are miniaturized per generation (for example, see Japanese Patent Application Laid-Open No. 2001-15743). A channel region is increased per unit area by miniaturizing cells, which leads to a reduction in on-resistance. As a result, loss during conduction can be reduced.
In a case of an n-type MOSFET disclosed in Japanese Patent Application Laid-Open No. 2001-15743, a channel is not formed in a p+ region when an n+ source region and a p+ contact region are disposed in a stripe shape. Accordingly, there is a limitation on a reduction of on-resistance.
As the technology for solving the above-mentioned problem, there is, for example, the technology of Japanese Patent Application Laid-Open No. 2009-81323. In the technology of Japanese Patent Application Laid-Open No. 2009-81323, in addition to the trench gate structure, the contact portion also has a trench structure (herein, referred to as trench contact structure). This leads to an increase in channel density per unit area in accordance with the same design rule, and hence a reduction in on-resistance is achieved.
In a semiconductor device having the trench gate structure and the trench contact structure, it is required that cells be miniaturized further while maintaining a low on-resistance. In a semiconductor device having the trench gate structure and the trench contact structure, in some cases, an electrical short circuit occurs between a gate and a source as a result of wire bonding of a source electrode. Therefore, it is desired that cells be miniaturized further while suppressing an electrical short circuit that occurs between a gate and a source.